EUROPEAN FPGA WITH RF CAPABILITIES (GSHE-3)

Description

This activity aims at the development of RF ADC, RF DAC and HSSLs IP cores; manufacturing, validation and rad-hardness evaluation of the IPs; integration with NG-Ultra core and update of NG-Ultra RF programming tools to allow configuration modes of the ADC/DAC and HSSL. The activity will be processed in Open Competition, subject to ESA's procurement rules and procedures adapted as per Financial Framework Partnership Agreement (FFPA) and Contribution Agreement and the tasks entrusted to ESA for GOVSATCOM.

Tender Specifics