FAULT-TOLERANT AND COMMERCIAL OFF THE SHELF-BASED ON BOARD COMPUTER (ARTES AT 4A.060)

Status

ISSUED

EMITS REFERENCE

Program

Advanced Technology

Price Range

> 500 KEURO

Description

Objective: Design, development, and prototyping of a fault tolerant and low cost On Boad Computer (OBC) with integrated Mass Memory(MM) for LEO and GEO applications

Targeted Improvements: Cost reduction and reduced development and production flow for the OBC andMM. The target is a recurrent cost of less than 10% of the current cost of components for a System Monitoring Unit. Possible performance improvements (e.g. mass, power, or volume reduction) from the use of Commercial Of The Shelf (COTS) parts are the expected secondary benefits.

Description: LEO orbits have less stringent requirements in term of radiation compared to those of GEO orbits meaningthe use of radiation tolerant components instead of radiation hardened parts can be considered. Reduced radiation hardness requirements allow innovative low cost solutions to be considered for the OBC and MM, whilst still providing reliable and fault tolerant onboard avionics. The aim of the proposed activity is to explore new technologies, processes, and packages targeting a cost, mass, and volume reduction compared to processors currently used within telecommunication missions. Whilst the solutions investigated may initially be most attractive for small, low-cost, non-GSO missions, the applicability to the conventional GSO market will be considered.An architecture for OBC and MM for telecom applications shall be studied and detailed. The use of new technologies and packaging solutions (e.g. plastic instead of ceramics) for nonvolatile memory, interfaces, FPGAs and processors shall be investigated. The useofCOTS parts with a minimum but effective screening shall be explored. A breadboard/prototype of aFault-tolerant and COTS-based OBC for low-cost applications shall be produced and tested.The proposed activity should consider the results of previous ESA studieson COTS elements (processors, memories, interfaces): e.g. the GSTP activities on High Reliability, High Availability, and High Performance Processors.The proposed Work logic is the following:- Requirement definition and trade-off with available technologies andsolutions for a low cost fault tolerant OBC+MM.- Architectural definition of a OBC + MM.- Detailed design of a OBC+MM (prototype).- AIT of OBC+MM prototype.

Tender Specifics