The objective of the activity is to derive an optimised star tracker design for telecoms based on the Faint Star detector with the main development focus on the optimisation of the use of the Faint Star on-chip functions and the star tracker (STR) software so as to provide a low impact, easy hosting of the s/w in the On-Board Computer (OBC).
Targeted Improvements:The objective is to reduce both a) power dissipation (up to -75% in case of active cooling removal), to ease the accommodation on the platform, and b) the recurring cost of one optical head, shrinking down the number of components per head.
Background: Improvements of platform competitiveness requires innovative changes at system level as well as unit level price reductions. For the STR, the development of the Faint Star detector is intended to lead to the possiblity to design and manufacture a low cost intelligent optical head consisting mainly of only a detector chip, the optics, and the support structure. What enables Faint Star to do this is the integration on chip of a wide array of initial image processing functions and a pixel array controller that enable to remove the need for a support ASIC/FPGA. Optimum use of such functions should enable the remainder of the software functions of the STR to be simplified to the point where a compact, but still robust, STR software may be produced and hosted in the central computer, thus saving the recurring cost of the processor and memories in the STR. To maximize the cost savings, the Thermo Electrical Cooler (TEC) should also be removed. The low noise, high sensitivity of the Faint Star detector, together with enhanced software is expected to make this possible.
Activity description: To prepare for such an implementation on a telecoms mission, the feasibility of the above outlined approach needs to be demonstrated. In particular this will require the optimisation of the use of Faint Star and its on-chip functions (including the comparison of these against full s/w implementations), the reassessment of the STR software processing and processing flow - including improvements needed to aid in the removal of the TEC, the optimisation of the STR software for being hosted in an OBC and the demonstration of the correct function and feasibility with a breadboard level series of tests to demonstrate the correctness of the control and functioning of the detector element (with commercial optics) and the ability of the s/w to be hosted in an OBC. It is expected that time and space partitioning (TSP) and auto-coding are likely to be beneficial to these endeavours.
Starting point: The starting point is the availability of Faint Star detector prototypes (mid 2014, GSTP G601-69EC),
Work logic: Overall trade-offs, such as needs in terms of surrounding electronics, Telecom mission EOL expected performance, possibility to avoid the need of active cooling. Breadboard design, assessment of on chip functionality, capabilities in terms of SW simplification (in both acquisition and tracking mode) keeping extreme robustness requirements vs solar flares. Test of the Breadboard using commercial optics. Development plan preparation for follow on activity (with REC and NREC cost estimation)
Procurement Policy: C(1) = Activity restricted to non-prime contractors (incl. SMEs). For additional information please go to EMITS news "Industrial Policy measures for non-primes, SMEs and R&D entities in ESA programmes".