MEMORY CONTROL SUB-SYSTEM FOR LOW EARTH ORBIT APPLICATIONS (ARTES AT 4G.035)

Description

The objective of the activity is to develop and test a technology independent and adaptable memory control sub-system for modern, integrated system-on-chip devices for low earth orbit applications. This will include radiation testing of low voltage, high speed memory technology. Targeted Improvements: Enabling integrated software defined radios utilising DDR3 and 4 memory; Resilience to radiation induced destructive events in LEO. Description: For missions such as telecommunication satellite constellations, where high performance and low cost are vital, industry requires modern MPSoC (Multi Processor System-on-Chip) and APSoC (All Programmable System-on-Chip) devices for their on-board computers, as these Field Programmable Gate Arrays (FPGAs), with integrated processors and programmable logic, offer unrivalled performance, flexibility and cost advantages. A weak point of these devices was their performance against Single-Event Latch-up (SEL), which was solved for low Earth orbit conditions by the introduction of the XQ series of the devices and a strict requirement for use of Double Data Rate 4 (DDR4) memories. In order to enable reliable use of these FPGAs, radiation characterisation of memory devices and their associated memory controller is required for Single-Event Upset (SEU) and Multiple-BitUpset (MBU) events. The availability of suitable memory devices and an associated memory controller will enable reliable use of modern, high-performance MPSoCs and APSoCs in payload and platform computers. This activity will design, manufacture and test a memory controller that will be able to perform SEU/MBU error correction on attached DDR 3 and 4 memories and APSoC/MPSoC memory interfaces. It will support the full recovery of the contents of a single memory chip in case of temporal loss due to memory SEL or single-event functional interrupt, thus masking outages due to radiation-induced memory errors. The activity will include Single-Event Effect (SEE) radiation testing (both under protons and heavy ions) of DDR4 memories to identify SEE failure modes and to quantify respectiverates, making use of available data from DDR3 radiation testing. The activity will deliver a reusable memory controller Intellectual Property (IP) core for use in MPSoC and APSoC designs.

Tender Specifics