Description
The objective of this activity is to develop, manufacture and test a reconfigurable and scalable avionics architecture that will integrate the majority of the spacecraft platform functions into a single reprogrammable System-on-a-Chip (SoC) Field Programmable Gate Array (FPGA), with embedded multicore processors. Platform functions include command and telemetry processing, attitudeand orbit control including star tracker processing,memory management, GNSS and various payload command and control interfaces.
Targeted Improvements: 50% reduction in the parts count for the On-board Computer (OBC); Centralising platform and payload telecommand and telemetry functions into the SoC; Reduction in the development and verification test time by at least 50%.
Description: Current telecom satellite On-Board Computers (OBCs) are based on space grade components having high overall cost and constitute fixedarchitectures, not adaptable to different mission needs. With cost being the dominant factor, due to series production, satellite constellations have adopted the use of automotive parts and software implementation of spacecraft platform functions, but this also results in afixed architecture and performances in the low range, prohibiting higher integration and mass/size savings.The introduction of APSoCs (All Programmable SoCs) integrating multiple microprocessor cores along with large Field Programmable Gate Arrays (FPGAs) and digital signal processing (DSP) blocks within the same chip, overcomes the above limitations, allowing for complex algorithms and applications to be implemented in a single chip. In the proposed activity these technologies will be used to develop a reference avionics Hardware/Software (HW/SW) architecture, integrating most platform and even suitable payload functions within a single chip. The different functional blocks will be mapped according to a HW/SW partitioning approach using a library of pre-developed, off-the-shelf,reusable hardware macros (IP Cores), and model-based system design methods for automatic code generation. The overall approach willreduce development and verification effort by 30-50%, hence enabling a faster time to market while also lowering schedule risks. Combined with the lower parts count and increased design reusability the overall cost could be also reduced by a magnitude. The deliverables of this activity will include an Engineering Model (at TRL5) consisting of a combined hard- and software demonstrator featuring, but not limited to, the following critical functions: telemetry/telecommand processing, AOCS (pre-) processing, reconfiguration,error protection and mitigation circuits, GNSS pre-processing, a Board Support Package incorporating Time and Space Partitioning and a preconfigured model-based design toolchain with representative models.
Tender Specifics