Christian Rohde
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33
Erlangen
91058
Beam hopping is an emerging technique to enhance flexibility, agility, and throughput of satellite systems. Due to adaptive activation/deactivation of beams according to the actual traffic demands, congestion problems are mitigated and the power efficiency is improved, compared to conventional systems with quasi-static illumination.
The project objectives are the following:
One of the key challenges of the project is the alignment between user data traffic, addressed beam and signalling the beam switching to the satellite in a synchronized manner. Next to that the provision of a DVB-S2X terminal coping with burst-wise data reception is of key importance and will have impact on the applied synchronization techniques. There will also be a reference terminal, which will provide means for alignment of the modulator transmission and the beam switching window with an accuracy of only a few symbols.
The entire testbed finally serves as proof-of-concept for the ground segment technologies required to enable beam hopping in future missions like Eutelsat’s Quantum project. The close cooperation between the technology providers Fraunhofer IIS and WORK Microwave with technical support from Eutelsat allows for a most realistic emulation of the Quantum payload and the optimization of the ground segment to enable a successful deployment after system launch.
On the other hand, the testbed will also be capable to host other payload characteristics or payload emulations by means of usage of standard L-Band interfaces for the signal transmission path as well as standard IP interfaces for the interaction between modulator and reference terminal.
The chosen waveform, DVB-S2X Annex-E super-frame format 4, is considered the best candidate in order to show a comprehensive proof-of-concept since it supports:
Other waveforms (no super-framing) or even other super-frame formats have not shown any advantage against the selected waveform.
The hardware testbed (as visualized in the figure) consists of four key components:
