The objective of this activity is to develop a breadboard device, in whatever technology deemed appropriate after a thorough analysis of available options, that demonstrates the feasibility of digital signal processor based equipment to directly output an RF signal. The targeted improvement is to eliminate the baseband (BB) or intermediate frequency (IF) to RF converters required to support digitally processed payloads, and digital modulators, thus saving mass, power and cost.
The translation from the digital processor’s output to either C-, Ku-, or Ka-band generates, apart from the envisaged RF output, a number of unwanted signals such as the image(s), local oscillator (LO) or carrier leakage, close-by spurious mixing products (e.g. LO±2IF, LO±3IF,..), harmonics and folded-down spurs. It is expected that the contractor implements techniques (e.g. adaptive biasing, multi-order cancellation technology, polyphase filters, multipath/multi-order cancellation, predistortion linearization, linear interpolation,…) for suppressing these unwanted outputs to levels that are acceptable for the transmit RF section of the payload.
Main challenges are; Dynamic range, power consumption, reference clock generation and input data bandwidth. Associated challenges due to limited dynamic range are; SFDR, NPR and accumulated phase-noise due to noise floor. Power consumption is a result of the extensive input data rate which is the major drawback of the current available RF DACs.
A direct sampling DAC could generate multiple frequency bands simultaneously if desired. The main benefit though is the flexibility (in what frequency bands to use and sub-channel bandwidth) and the high order of integration. If the overall dynamic range of the DAC is large enough, output power control per sub-channel is also achievable. The oversampling gain also works in favour for multi-Gigasample DACs by increasing the effective-number-of-bits.
Targeted accumulated usable bandwidth with current technology is set to 500 MHz bandwidth, distributed at any desired frequency (within assigned band). This limitation comes from the available dynamic range together with regulatory requirements. Usage of up to Ka-band is targeted, enabled by a sample rate of 67 Gsps, low intrinsic jitter and high analogue bandwidth.
The system architecture is based on an evaluation platform from a vendor supplying these types of components. The transmitter line-up is analysed and characterized but not build. The system setup aims to enable verification of a multiple set of user cases proving, when verified, the usability of the RF DAC component with the limitations of the current available technology.
This study has three phases:
A device from MICRAM was selected for this study and a development board was used for all tests. The MICRAM device and its successors are capable of direct sampling, but it is obvious that the DAC should be integrated in another device since the power consumption of the SerDes data lines is very high. All tasks are performed.