- Partnership Projects
- Core Competitiveness
- Future Preparation
- Space Solutions
- How to Apply
- Our Projects
Space Engineering (SE) is strongly motivated to develop ground-segment products compliant with the new DVB-S2 standard.
To achieve this objective, SE has conceived the DEDICATION project with the aim to perform critical developments that will have a clear commercial finalization.
The targeted markets are expected to develop in two contexts:
To test the critical developments envisaged above, the DEDICATION project aims to develop DVB-S2-Test Bed (DTB), a comprehensive laboratory facility within which the key DEDICATION Products are fitted.
DTB creates a realistic environment in which to thoroughly validate those Products.
The DEDICATION project is intended to perform:
After years of successfully acquiring important capabilities in the development of state-of-the-art equipment, SE is currently turning such equipment into proper commercial products.
After some successful examples with DVB and TT&C, SE now looks with great interest to DVB-S2, representing very important occasion for the development of commercial products.
There are two distinct DVB-S2 markets SE plans to tackle: that of User Terminal (UTs), and that of Hub.
SE intends to pursue those markets primarily in the KabSat context (the Ka-band satellite system that is being devised with the main objective to serve the Italian Public Administration telecommunications needs). In fact the DEDICATION project represents a fundamental step with regard to the development of the innovative KabSat ground station equipment, and the financial support that ASI has granted to that project is therefore to be seen in tight synergy with the above cited KabSat RFP.
SE however also intends to address the more general context of wide-band satellite systems.
The overall SE DVB-S2 product development strategy is subdivided into two phases:
Phase1, coinciding with the DEDICATION project, will result in the so-called "DEDICATION Products", essentially consisting of a set of IP cores implementing the DVB-S2 Hub and User Terminal (UT).
Phase 2, to be considered under the already cited ASI KabSat development program, aims at the so-called "Target Products", FPGA/ASIC based, which have a much greater market potentiality in terms of sale count and revenues.
Said products will be developed by SE in partnership with a manufacturer of RCS equipment which will be selected in concertation with the other companies participating in the core KabSat development team.
The DTB basically comprises:
The DVB-S2-FL comprises a state-of-art DVB-S2 modem prototype, supporting Constant Coding and Modulation (CCM) mode, Variable Coding and Modulation (VCM) mode and Adaptive Coding and Modulation (ACM) mode. The modem includes the ACM router functionality required for fully exploiting the DVB-S2 ACM operating mode capability.
Hence, the modem also includes the following functions:
The VHBCS implements emulation of carrier Doppler shift, HPA non-linearity, IMUX / OMUX filters, interference (adjacent channel and co-channel), tropospheric fading and thermal noise over a bandwidth of 100 MHz. The VHBCS input and output and output interfaces are at 140 MHz IF.
The Return Link is emulated by a direct connection (at IP level) in charge of transferring ACM management signalling in addition to support any return application traffic.
The DTB allows real time testing of physical layer and system performances. Traffic generators emulating real Internet applications. The demonstrator thus permits to validate physical layer performance in a realistic non-linear satellite channel. It also allows validation of the selected physical layer adaptation and MAC scheduling algorithm including their impact on application QoS (e.g. throughput and latency). Finally, the effects of fading on QoS can be also assessed.
The DEDICATION project includes five Technical Tasks and a Management Task:
Tasks are subdivided into a total of 39 Work Packages. WP responsibility is assigned to 11 highly qualified Key Persons. The project duration is 18 months and is organized as follows:
The initial activity of review and analysis of system requirements is concluded with the Baseline Design Review. On BDR latest results are provided about the DVB-S2 modem/codec performances.
The activity to implement a detailed SW simulator of the demonstrator based on the Generic Stream is completed in Phase 1. The IDR concluding the Phase 1 was held on October 2006.
The Phase 2 started in January 2007 with a revision of the GS architecture aiming at improving the system throughput efficiency and with the acquisition and evaluation of the commercial hardware to implement the upper layer functions.
In September 2007 the Upper Layers elements were implemented and the individual stand-alone testing was started.
In May 2008 the physical Layers elements were characterized by SW simulations and their implementation in HW was completed up to a level allowing pre-integration with Upper Layer for at least 5 out of the 8 MODCOD supported by the current implementation. All the final ancillary HW design activities aiming to provide the Dedication DVB-S2 station in a single 19” Rack i.e. back-plane, clock generation and distribution were completed and their manufacturing is on going.
The Upper Layers integration activity is completed (the Physical Layer replaced by a stub) with the verification of the performance at fixed modcod and with the ACM control to change dynamically the modcod.
Ping request (ICMP)and video streaming (UDP) are used to generate the wanted traffic during the ULs integration.
In December 2008 the activity was completed with the successful experimentation of real Internet services (video streaming, web browsing) in a comprehensive channel and traffic environment including three IP networks: DTB, INTRANET, INTERNET.
The system can be analogously made available via internet to external users in order to make experiments on other services and configurations of interests
The DTB system allowed the development ad the verification on realistic environment of some standard blocks of the of PL and MAC layer, such as:
These functionalities have been implemented in medium performance FPGAs and they are ready to be implemented in latest technology FPGAs and in ASICs.