Design & Build Ka Band Transceiver Chipset Design & Build Ka Band Transceiver Chipset


Arralis have designed and built Ka Band Core Chip MMICs for Low Earth Orbit (LEO) satellite communications applications. Each chip has been packaged in QFN (Quad Flatpack No Leads). A demonstrator transceiver board was developed for ease of demonstration.

Arralis have developed the technology to TRL4 whereby we have fabricated & packaged QFN MMICs and validation testing has been carried out in a laboratory environment.

The types of problems solved by this product include the basis of a LEO ground to satellite communications network. This network would allow unimpeded low-cost data access across the globe.

This project lead to the design and build of 5 x core chip (or multifunction) MMICs for operation in the satellite uplink and downlink frequency bands (~29GHz and ~19GHz). As the MMICs are highly integrated and included functionalities such as VCOs (with locking supplied by a low frequency PLL), LO amplification, LNAs, PAs and mixers over both frequency bands, a simplified solution for chip integrators is supplied. All core chips are packaged using a QFN (Quad Flatpack No Leads) packages which makes integration even easier.

A Transmit (TX) and Receive (RX) demonstrator transceiver reference board illustrates the ease of adoption of this technology.



To implement a multifunction MMIC with parameters as varied as NF, phase noise and power, the choice of MMIC foundry process which offered a compromise between all these parameters was difficult. Likewise, the avoidance of detrimental coupling between the different sections of the core chip MMICs was also difficult and required a considerable amount of simulation effort to ensure that the chips worked acceptably.


The combined receiver/ transmitter chips which Arralis have produced is one of the major benefits of the development. Competitors have an extensive range of satellite products but none with this dual capability. Other similar products operate within the Ka band frequency; however, these are not end user- friendly as the final device in which the chips will be used requires a great deal of self-integration. This becomes costly and time consuming for the end user as well as adding to the existing development work.

‘New’ space companies have sighted vertical integration as a critical component of the design process in future missions. The more integrated the solution, the closer to platform, which ultimately gives the greatest competitive advantage. Our integrated core chips will have a key strategic advantage for these companies with their ease of integration. 


Key Performance Factor


Frequency Range

Full Uplink and Downlinks 19-22 and 27-31GHz

Power Output

Complete chip has 200mW output leaving end user flexibility for final stage

Noise Figure

2dB LNA/p>


14dBm, 24GHz, -80dBc/Hz @1MHz (locked)

Complete Transmitter


Complete Receiver


System Architecture

The basic RF system architecture is shown below:


Phases and milestones of this project include:

  • Design, fabrication and testing of the individual MMICs
  • Design, fabrication and testing of the core chip MMICs
  • Packaging and testing of the QFN MMICs

Development and testing of the demonstrator transceiver board

Current status

The project has been completed. The packaged QFN MMICs performance were satisfactory when compared to their bare die MMIC equivalents. The Transmit (TX) and Receive (RX) demonstrator transceiver board has also been finalised.


ESA Contacts

Status date

Wednesday, December 19, 2018 - 11:54