Enhanced Output Command Driver (EOCD)


The objective of the project has been to design, develop and validate a prototype of a mixed signal ASIC (EOCD) to be used as output command driver in on board computers. 

Specific features of the development are related to design in a high voltage technology taking into account ESD and radiation tolerance.   


 The key issues of the project were implementation of the output command driver in a high voltage ASIC technology, I3T80 from OnSemi. The design has also addressed key requirements related to ESD, radiation and SEE. 


 The use of output commands in on board computers and data handling systems is a common task. Up to now this functionality has been performed by an ASIC that is now longer available. The EOCD provides means to increase level of integration, reduces needed PCB area and reduces power consumption compared to other solutions based on discrete implementation.  


The EOCD ASIC is a general purpose device, in the first place intended for generating HPC pulse commands according to [ECSS].
The EOCD can provide 32 pulse commands of up to 300mA, compatible with LV-HPC and HV-HPC according to [ECSS].
In order to eliminate risk for spurious commands, special redundant and failure protection functions are implemented to assure ‘fail silent’ behaviour. This includes double serial switches for each output.
Slope control compatible with [ECSS] HPC is implemented. The slope can also be adjusted by means of a special input.
The EOCD can be operated in three different modes:
-    Parallel mode: In this mode each 2 outputs are controlled by a dedicated logic level input pin, i.e. it is operating like in HC mode. A possible usage is voltage level conversion of up to 16 signals.
-    CPDM mode: This mode is especially designed for direct interface to the CPDM format in CROME or the HlcSer format in M2. Address straps are used to allow several EOCD sharing the same serial control signals. Outputs can operate in either Std or HC mode.
-    BSD mode: In this mode, the EOCD is controlled by standard BSD (ML16/DS16) according to [ECSS]. Outputs are then operating like in HC mode.
The outputs are grouped in 4 groups, each with one HvIn input (2 pins) and 8 HvOut outputs. The 4 HvIn inputs are independent and can be biased with different voltages if desired. It is then of course also possible to bias them with the same voltage but via individual current limiters.
Example of usage together with CROME ASIC.


 The development was divided in the following work packages:

WP01: System engineering
WP02A: Design Cell Library
WP02B: Design Circuit
WP03A: Provide test Equipment
WP03B: Test/Validate prototypes

The project started in September 2011 and the tape-out for MPW occurred during the last quarter of 2012. The manufactured EOCD Demo ASICs were received in April 2013 and the validation was completed in December 2013.    

Current status

 The EOCD DEMO ASIC validation has been completed. The next steps are related to optimising the design based on findings from the so far completed work in order to have version that can be used in flight applications. This includes formal industrialisation of the EOCD ASIC 

Status date

Thursday, December 17, 2015 - 11:31