High Throughput Processor for Future Bent-Pipe Broadband Networks


This project aims to increase the competitivity of future satellite broadband access systems by dramatically increasing the capacity per spacecraft.

A target capacity of 50 GHz is envisaged, equivalent to 200 times the processed bandwidth of Inmarsat 4, which represents the current state of the art in transparent processed payloads. Multiple spot beam coverage will be required to achieve the necessary antenna gain and frequency reuse. In order to support the necessary flexibility in channel to beam routing, frequency mapping and channel sizing, a complex digital processor will be needed as a central element of the payload.


Such a system will require significant advances both in enabling technologies and in terms of processor algorithms and architectures. Each aspect will be investigated in detail to produce a set of candidates to be traded off in a realistic system and payload context. The objective is to obtain the optimum balance between performance, flexibility and capacity over the whole payload to maximise the competitive advantage. The selected architecture will be encapsulated in a simulation model to demonstrate the processing algorithms and system performance taking into account the effects of the overall payload.


Among the many challenges faced by a high capacity design, some key issues are:

  • Minimisation of power to fit within budget expected of future platforms,
  • Antenna design to give high performance on ~200 user beams,
  • Q-band technology for gateway beams,
  • Filter technologies,
  • Analogue and/or digital beamforming,
  • Flexibility requirements for routing,
  • Interconnect within the digital processor,
  • Use of optical technology in the processor,
  • Wideband data conversion,
  • Efficient digital algorithms for demultiplexing, switching and beamforming,
  • Processor packaging technology and thermal management.


The chief benefit of such a system is the huge competitivity increase in providing two orders of magnitude greater capacity on a single spacecraft while still maintaining the flexibility afforded by an on-board digital processor. The study provides an opportunity to consider novel transparent payload processing architectures optimised for high bandwidth and an access type of mission using technology that will become available over the next few years. One output of the project will be a complete payload simulation tool that will facilitate the trade-offs to be performed for such a high throughput system.


The overall mission scenario is to provide broadband remote access to terrestrial networks by satellite. The system assumes asymmetric link capacities typical for internet access, with 40 GHz forward and 10 GHz return processed bandwidth per satellite. High rate TDM carriers would be suitable for the forward link with MF-TDMA for the return, although the payload will be transparent.

In general, such a system would be used by multiple network access providers under the supervision of a single network operator. For such high capacities the Ka-band is the logical choice for the user links while Q-band is a possibility for the gateway side. The satellite will provide regional (e.g. European) coverage from geostationary orbit with up to about 200 beams. A high level of frequency reuse will be needed to support the target capacity, most likely using ACM to mitigate co-channel interference between beams.

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More detailed system parameters are to be determined during the course of the study. Among these, flexibility of connectivity and routing granularity are parameters that will play an important role in the overall size and complexity of the processor. This must be traded off against the benefits they provide to the eventual operator.


The space segment is required to demultiplex the FDMA signals, route channels with a fine granularity and recombine them on a beam basis. The appropriate beamforming must be applied for gateway and user links. The satellite provides independent forward and return links with no requirement for cross-connection between the two.


The work is broken down into two phases consisting of the following tasks:


Task 1.1: Reference system scenario definition
Task 1.2: Critical review of payload and processor technologies
Task 1.3: Critical review of processor architectures
Task 1.4: High level processor architecture definition


Task 2.1: Detailed processor design
Task 2.2: Processor design validation by simulation

Current status

The project was successfully completed and a Final Presentation made at ESTEC on 29 November 2005.


Status date

Tuesday, March 21, 2017 - 10:35