HPLO High Purity LO Source

Status date

The target of this development is to improve the phase noise of a fixed frequency oscillator by use of STW delay line and optimized phase/frequency locking and phase noise reduction electronics.

The activity will be based on previous work performed at Kongsberg Norspace (SAWRES) where unique performances were demonstrated, yet at low TRL level (TRL-4).  The aim in this activity is, amongst others, to implement and test a complete LO Elegant Breadboard.

The most challenging requirement of the unit is the phase noise specification. The requirement induces challenging performance demands on some of the building blocks, especially the phase detector and the VCO. Also the internal OCXO needs to be focused on and a very low phase noise performance is needed.


In the previous work performed, a VCO with state-of-the-art phase  noise performance was demonstrated. Even if superior phase noise performance was shown in the previous project, additional 5-7dB improvements is needed to comply with the phase noise requirement of the complete phase locked loop local oscillator for this program. The main parameters that are further optimized are the VCO signal power, noise characteristics and the delay in the STW delay line.


The improved Local Oscillator (SPLO; Sampling Phase locked Local Oscillator)) will enable future payloads that will use higher order modulation schemes requiring more stringent phase noise requirements  for both frequency conversion and low jitter sampling clocks in broadband data converters.  


The SPLO architecture is optimal for low phase noise design and can be used when the output frequency is a multiple of the input reference frequency. The technique uses a harmonic mixer known as a sampling phase detector, instead of using digital dividers and phase detector in the phase locked loop. This is an advantage for the SPLO design, as prescaler and divider circuits with their noise contributions are not needed in the loop. In the sampling phase detector the VCO is locked on the harmonic of the reference frequency closest to the free-running frequency of the VCO. The excess noise is very low giving close to the theoretical minimum of the multiplied reference. This configuration also benefits from a high Q STW delay line based VCO (VCSO), which in addition to very low phase noise also has the needed bandwidth limitation to prevent false locking (locking to the wrong harmonic). 


The selected base line is the Direct Phase Error Detection using a SPD based PLL. The implementation is referred to as an SPLO (Sampling Phase locked Local Oscillator). This is an architecture that is based on analogue implementation. It is also well suited for PCB implementation with some of the elements made as hybrids. The block diagram of the base line SPLO architecture is given in Figure 3‑11. The configuration of the elements in the VCO hybrid will be optimized during the design process, but an example of how it might be is given for illustration purpose.

Figure: Block diagram of baseline SPLO architecture


The work is split in five tasks

Task 1: Literature survey and baseline design

Task 2: Design of ciritcal blocks and breadboarding

Task 3: Detailed design of EBB

Task 4: Manufacturing and test of EBB

Task 5: Conclusions and way forward

Current status

The program is now completed.

After initial investigation and critical breadboarding, the detailed design of all building blocks were established. The optimised building blocks are fabricated, characterized and verified. Two complete VCOs and later also a complete LOs (PLL) Elegant Breadboards (EBB) were assembled and tested. Based on the reported result the TRB/Final Review was held.

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