Joint Turbo Decoding and Carrier Synchronisation


The activity "Joint Turbo Decoding and Carrier Synchronisation" was carried out by Advantech Satellite Networks and its partners Turbo Concept and Eurecom.

The main objective of this project was to develop and validate new techniques that enable power efficient transmission for satellite receivers. While the algorithm investigations and their performance evaluation were not limited to any specific air interface, the main focus was on DVB-RCS and DVB-S2 compatible receivers. Due to the dominant role of conventional carrier synchronisation techniques in the receiver performance degradation, the work was directed towards improving this aspect; i.e., the frequency and phase synchronisation algorithms.

In the first part of this project, a set of algorithms, providing significant improvement in carrier synchronisation accuracy, was selected. Carrier synchronisation algorithms were developed that can take advantage of the iterative decoding process for turbo codes and LDPC codes in order to enhance the performance, especially at low coding rates and for short bursts and in the presence of severe phase noise.

In the second part, the selected algorithms were implemented and tested in hardware. The final validation included lab testing for a pre-selected set of transmission modes.


  • The impact of synchronisation on the performance of burst mode receivers operating at low coding rate;

  • Investigate carrier synchronisation techniques that are robust against phase noise and carrier frequency offset;

  • Trade-off between algorithm complexity and achievable performance;

  • Trade-off between the hardware throughput and the achievable performance.


  • We established a performance baseline for the DVB-RCS code, compared to theoretical bounds (Channel Capacity, Sphere packing and union bounds) and determined the best achievable performance using classical synchronisation schemes with optimised parameters for BPSK, QPSK and 8-PSK modulation.

  • We performed a critical review of the published or otherwise known joint iterative decoding and synchronisation algorithms and selected the most promising candidate schemes. As part of this, we

    • Investigated a set of joint synchronisation and decoding (JSD) algorithms, derived as an "evolutionary" extension of known classical algorithms for DVB-S2, DVB-RCS and extended DVB-RCS air interfaces.

      Investigated a state-of-the-art algorithm derived from an approximation of the Belief Propagation algorithm, known as the "Colavolpe-Barbieri-Caire" (CBC) algorithm for DVB-RCS and extended DVB-RCS air interfaces, and even for DVB-S2.

  • We built simulation software to assess the performance of the selected schemes and finally compare their performance and complexity.

  • We carried out VHDL design of the selected algorithms and validated the developed design in FPGA based hardware platforms.

Extensive simulations and complexity assessments, later confirmed by implementation and testing in the laboratory, have confirmed the performance improvement and implementation feasibility of such techniques. The "evolutionary" techniques were implemented for a demodulator for the current DVB-RCS air interface and straightforward extensions of this, such as the use of BPSK and 8PSK modulation. To maximise practical utility, the CBC algorithm was successfully implemented using DVB-S2 air interface, jointly with an LDPC decoder.

The main conclusion is that the techniques based on evolution of current techniques bring very worthwhile improvements for DVB-RCS transmissions, in particular for short bursts, at low signal-to-noise ra


The powerful coding schemes employed in DVB-S2 and in the DVB-RCS return link potentially provide transmission performance in terms of power efficiency very close to theoretical baselines. However, in some circumstances the limited accuracy of conventional synchronisation circuits in the receiver prevents the fulfilment of this potential. The use of power efficient transmission schemes is essential to mitigate the impact of the rain fade without introducing large rain margins in the link budget. Such margins increase the cost of the user terminal considerably. The transmissions used during rain fades typically operate at low signal-to-noise ratio and often use low data rates, resulting in increased susceptibility to impairments such as frequency offsets and phase noise. The synchronisation performance limitations affect considerably the use of low coding and data rates as a countermeasure against the rain fade. Overcoming these limitations is therefore one important element of the overall strategy to create robust DVB-S2/DVB-RCS systems that can offer a high quality of service.

Traditionally, demodulation (synchronisation) and decoding are treated as two distinct operations. This is partly due to legacy from the concatenated-coded demodulators, and partly due to limitations of available decoder cores (which do not do any part of the demodulation). At high carrier frequencies (in particular, at Ka-band), RF power amplifiers are major cost drivers for the user terminal. There is therefore a strong interest in developing power-efficient solutions, in order to facilitate the deployment of interactive multimedia systems in the consumer market where the user terminal cost is of paramount importance.

Furthermore, the phase noise characteristics of the low-cost terminals, operating at low baud rate, can be worse than predicted for example in system guidelines. One of the main objectives of this project was to develop robust synchronisation schemes that can tolerat


  • Define and justify the system and channel parameters for the reference DVB-RCS system. Analyse the performance of the best known classical carrier synchronisation;

  • Perform a critical literature review of the published joint turbo decoding and synchronisation algorithms;

  • Select the most promising candidate schemes;

  • Build simulation software to assess the performance of the selected schemes and finally compare their performance and complexity;

  • VHDL design of the selected algorithms;

  • Validation of the developed design in FPGA based hardware platform.

Current status

The initial goals have been achieved and the corresponding activities completed. Extension of the work to consider burst detection and timing synchronisation is expected to start in late 2006 or early 2007.


Status date

Tuesday, March 8, 2011 - 13:04