S-Band Receiver Chipset

  • Status
    Ongoing
  • Status date
    2011-11-25
Objectives

The S-Band Receiver Chipset is a fully standard compliant DVB-SH Demodulator. DVB-SH is a standard for a hybrid digital broadcasting system, composed of a Satellite Component (SC) and a Complementary Ground Component (CGC).

There are three main characteristics of the DVB-SH standard that make the S-band Receiver chipset a very attractive product:

  • In a world which is getting mobile, the DVB-SH standard offers television services to handheld devices.
  • For a society that demands access to more and more information digital broadcasting achieves a better spectral efficiency allowing more content to be transmitted.
  • For people becoming increasingly exigent in terms of quality of service, the hybrid system architecture provides an optimal overall coverage.

The primary goal of the S-Band Receiver Chipset project is the development of a fully standard compliant DVB-SH Demodulator and the DT4500, a test signal generator for all configurations available in the DVB-SH standard.

The DVB-SH demodulator IP has been optimized for best user experience in mobile scenarios. It can be mapped to virtually any ASIC or FPGA technology. The configurable and flexible architecture enables an optimal trade-off between complexity and functionality depending on the use-case.

The DT4500 DVB-SH Signal Generator is a test signal generator for the full DVB-SH standard. It features live physical layer encoding for two TDM and one OFDM path using MPEG-TS files as an input. An integrated 18-tap multipath channel emulator is available on the OFDM path. Stationary or time variant flat fading can be applied to all paths. Noise generators can individually be configured for each of the RF outputs.

Challenges

The key issues being addressed are:

  • Receiver Development: specification, design, and development of a DVB-SH demodulator capable of handling the complete DVB-SH standard (SH-A, SH-B, Class 1, Class 2).
  • Test Equipment Development: specification, design, and development of a signal generator and channel simulator for DVB-SH.
  • Receiver Characterization and Validation: validation and performance characterization of the DVB-SH Demodulator using the Test Equipment.
Benefits

The main benefits of the DVB-SH Demodulator IP to be developed in this project are listed below.

  • Optimized for Mobility: Based on the feedback from participation to numerous field trials throughout Europe, the DVB-SH IP has been optimized for best user experience in mobile scenarios.
  • Easy to Integrate: Being a soft IP, the DVB-SH demodulator can be mapped to virtually any ASIC or FPGA technology.
  • Flexible Architecture: The configurable architecture provides many options for a trade-off between complexity and functionality.
  • Standards Compliant: Our experts are actively contributing to the DVB-SH standard and participate to various projects aimed at validating the complete DVB-SH transmission chain.
  • Based on Expertise and Experience: The DVB-SH IP is based on more than a decade of experience in the successful development of demodulator ICs for satellite based digital broadcasting systems.
Features

To cope with the multitude of possible system configurations the DVB-SH Demodulator developed in this project offers a flexible, configurable, and extensible soft IP capable to support the full range of DVB-SH system configurations and waveform parameters.

The key features are:

  • Field proven DVB-SH OFDM demodulator with scalable FFT size (2k – 8k).
  • Field proven DVB-SH TDM demodulator.
  • Mobile DDR memory interface supporting interleaver memory sizes up to 2 GBit.
  • Full Support for code combining (CC).
  • Diversity support via maximum ratio combining (MRC).
  • High-throughput turbo-decoder.
  • Fully integrated MPE decapsulator with MPE-FEC and IFEC support.
  • High-speed serial interface.
  • Optional host interface to internal Reed-Solomon decoder.

Being a soft IP designed for maximum flexibility and performance, the customer can tailor the IP for a variety of application scenarios:

  • Extensible/adjustable to customers specific needs (soft-IP).
  • Configurable number of OFDM/TDM demodulators.
  • Adjustable size of interleaver memory.
  • Companion chip interface for additional diversity options (available upon request).
  • Integration services to adapt interfacing to customer requirements (available upon request).
Plan

The project is split into two phases. Specifications are elaborated in Phase 1, while design and implementation is carried out in Phase 2.

Phase 1 “System Specification” is concerned with the following tasks:

  • System engineering.
  • Specification of chipset IP, validation test-bed, and test equipment.

Phase 2 “Implementation” comprises of:

  • Module design.
  • Implementation.
  • Integration.
  • Validation.

Two target platforms were used for development and validation of the DVB-SH Demodulator IP.

  • A commercial real-time emulation platform for integration, validation, functional and performance measurement.
  • An FPGA-based field-test platform, the Embedded Module.
Current status

The project is completed.

Documentation

Documentation may be requested

Last update
2024-04-25 15:41