SBVT - Space Based VDE Transceiver

Objectives

The goal is to develop an engineering model of a VDE-SAT transceiver payload, implementing full VDE-SAT support (uplink and downlink protocols as well as ASM).

Challenges

  • Develop a mature VDE-SAT transceiver based on the evolving VDES standard
  • Increased need for FPGA resources in order to support multi-channel reception of ASM and VDE-SAT in parallel
  • High transmit output power requirements while aiming for low power consumption in order to fit small-sat missions
  • Complexity of including simultaneous VDE + ASM reception support
  • Out-of-band interference, specifically towards the Radio Astronomy bands

Benefits

The Space Based VDE Transceiver will offer full VDE-SAT functionality, and is an expansion of our current VDES satellite products. 

Features

  • Reception of 2 ASM-SAT channels
  • Reception of 3 VDE-SAT uplink channels
  • Transmission of up to 3 VDE-SAT downlink carriers
  • Handling of VDE-SAT signalling (reception, processing, transmission)
  • VDE-SAT uplink resource allocation for assigned slots

System Architecture

The Space Based VDE Transceiver is enclosed in a mechanical unit of size 75 x 145 x 176 mm with a weight of 1500 g (TBC). The power consumption is TBC W. The unit supports multiple antenna configurations with up to 1 Tx and 4 Rx separate antennas, and full-duplex operation (using external duplexer). Output power is 33 dBm (TBC) in single-carrier operation and 39 dBm (TBC) in multi-carrier operation.

The hardware design of the payload consists of two PCBs where the analog RF frontends and power supply is on an interface board, while the ADCs, FPGA and transmitter is found on a secondary transceiver board. The payload supports cold redundancy using a 2nd transceiver board. Xilinx Ultrascale+ is used as the FPGA solution, incorporating two Microblaze softcore microprocessors.

Communication with the satellite on-board computer is through a RS-422/485 interface. SpaceWire and CAN-Bus is supported in hardware and will be added in the future.

Plan

The project consists of the following phases and milestones:

  • Requirements consolidation – SRR
  • Design phase – DR
  • Manufacturing phase and test planning - TRR
  • Verification phase and completion – FR

The project is currently in Design phase.

Contacts

ESA Contacts

Status date

Friday, November 2, 2018 - 11:02