The goal is to develop an engineering model of a VDE-SAT transceiver payload, implementing full VDE-SAT support (uplink and downlink protocols as well as ASM-SAT).
- Develop an on-board transceiver based on the evolving ITU Standard for VHF Data Exchange System (VDES)
- Increased need for FPGA resources in order to support multi-channel reception of ASM-SAT and VDE-SAT in parallel
- High transmit output power requirements while aiming for low power consumption in order to fit small-sat missions
- Complexity of including support for simultaneous reception of multiple channels of different types (VDE-SAT/ASM-SAT)
- Out-of-band interference, specifically towards the Radio Astronomy bands
The Space Based VDE Transceiver will offer full VDE-SAT functionality and is an expansion of the current Kongsberg Seatex VDES satellite products.
- Reception of two ASM-SAT channels
- Reception of three VDE-SAT uplink channels
- Transmission on up to three VDE-SAT downlink carriers
- Handling of VDE-SAT signalling (reception, processing, transmission)
- Receiver beamforming capabilities on up to four antennas
- I/Q signal sampling on up to nine channels
- Maritime VHF band spectrum analyser functionality
The Space Based VDE Transceiver is enclosed in a mechanical unit measuring 168 x 140 x 52 mm (L x W x H) with a mass of 1200 g. The payload supports multiple antenna configurations with up to 1 transmit and 4 receiver antennas. Maximum nominal output power is 33 dBm in single and multi-carrier configuration (saturated output power is 39 dBm).
The hardware design of the payload consists of two PCBs where the analog RF frontends and power supply is on an interface board, while the ADCs, FPGA and transmitter is found on a secondary transceiver board. The payload optionally supports cold redundancy using a second transceiver board.
Communication with the satellite on-board computer is through an RS-422/485 interface. SpaceWire and CAN-Bus is supported in hardware and can be added as firmware upgrades in the future.
The transmitter and receiver architecture is implemented as FPGA logic, including the turbo forward error correction (FEC) decoder/encoder. Support has been implemented for VDES waveforms LCI 4, 20-24, 31-32.
The project consists of the following phases and milestones:
- Requirements consolidation – SRR
- Design phase – DR
- Manufacturing phase and test planning - TRR
- Verification phase and completion – FR
The project is COMPLETED.
The main achievements of the project are:
- Designed a powerful and flexible VDES transceiver payload for use on microsatellites in low earth orbit featuring state-of-the art processing capabilities and high radiation resilience
- Developed, manufactured and tested a prototype of the new VDES transceiver payload
- Designed and tested a novel, highly power efficient power amplifier for use in the VDES transmitter in the payload
- Designed and implemented in FPGA new modules required for the VDES transceiver
- VDE/ASM multi-carrier receiver front-end
- VDE/ASM multi-carrier burst receiver
- VDE/ASM compatible Turbo decoder
- VDE multi-carrier transmitter with Turbo encoder
- Verified VDE/ASM uplink specification from new VDES specification and contributed to updates and corrections of the specification
- Made detailed design for VDE-SAT downlink specification and contributed design and new waveforms to IALA for inclusion in VDE specification.
