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StatusOngoing
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Status date2011-05-31
The project target is the development of a DVB-SH demodulator compliant with DVB-SH standard.
The s-band receiver chipset project objective is the development of a DVB-SH demodulator fully compliant with the DVB-SH standard. Moreover the demodulator is a multi-standard receiver capable of receiving DVB-SH, DVB-H and DVB-T signal.
The receiver development is targeted towards mobile reception, with integral support of code combining, antenna diversity and high Doppler resilience to enhance quality of reception in all conditions.
The receiver also supports the features newly added to the DVB-SH standard:
- 2.5 MHz bandwidth.
- Low-latency services.
A prototype of the demodulator has been built based on FPGA architecture having the complete features of the demodulator available for field-testing as well as for laboratory performance tests.
The key issues addressed in the project are:
- Design of a multi-standard demodulator being able to support the full specification of the DVB-SH/DVB-T and DVB-H standards.
- Development of a demodulator FPGA-based prototype being able to fully implement all the demodulator requirements.
- Testing all the demodulator features (which implies thousands of different configurations), which implied the development of an automatic test bench for allowing running tests in batch-mode.
- Full characterization of demodulator performance in a wide range of mobile and fixed reception scenarios and in different configurations (TDM-only reception, OFDM-only reception, Code-Combining, diversity reception, etc).
The main benefits of the project are:
- Multi-standard receiver.
- Fully tested in the field.
- Especially suited for challenging mobile reception conditions with best-in-class Doppler performance.
- Wide range of host interfaces, to allow easy integration in a wide range of different host systems.
- Possibility of running in stand-alone mode with direct IP video streaming through Ethernet.
- Ready for mass-market manufacturing.
The DVB-SH standard supports different system configurations (DVB-SHA, DVB-SHB), each with different profiles (Class-1 and Class-2 interleaver profiles), apart from this the DVB-SH standard defines the use of MPE-IFEC at the link layer, and the standard has been updated with support for low-latency services and extra bandwidths. Apart from this the receiver is a multi-standard receiver supporting DVB-H/DVB-T and DVB-SH.
To cope with all those requirements in a flexible way the receiver employs a flexible fully parameterizable architecture that has been extensively tested both in field trials and in laboratory. It has the following features:
- Highly flexible physical layer:
- OFDM demodulator supporting all FFT sizes (1k, 2k, 4k, 8k) and Cyclic-prefixes (1/4, 1/8, 1/16, 1/32). All defined bandwidths are supported (1.7, 2.5, 5, 6, 7, 8MHz).
- TDM demodulator supporting all modes defined in the standard. All defined bandwidths are supported (1.7, 2.5, 5, 6, 7, 8MHz).
- Code combining support.
- Low-latency support for both waveforms.
- Antenna diversity as integral part of the demodulator.
- Link layer features:
- DVB-H MPE-FEC support.
- MPE-IFEC support.
- Highly flexible MPE decapsulation with enhanced filtering capabilities.
- Wide range of host interfaces for maximum flexibility while connecting to a wide range of hosts, and for stand-alone use:
- High speed serial interfaces: SPI and SDIO.
- External memory controllers for connecting to external memories when Class-2 time-deinterleaver profiles are required.
- Ethernet interface.
- Serial or parallel transport stream output interface + I2C control interface (for simple connection with hosts having transport-stream input).
- Smart-Card interface, if security options are desired.
The receiver architecture is targeted towards ASIC integration for mass-market production, but it also has FPGA technology in mind for initial evaluation/low volumes. Moreover an FPGA prototype has been developed to be able to exercise all the features of the receiver in field and lab tests.
The project is divided in three phases:
- Phase 1: System Requirements review and IP/Chipset definition. During this phase the analysis of the requirements is performed and the requirements of the demodulator are delineated.
- Phase 2: This task deals with the design of the demodulator and the implementation of the FPGA prototype, together with the testing of the prototype in the laboratory.
- Phase 3: During this task the demodulator is prepared for mass-market manufacturing in an ASIC technology.
The project is completed.