The project target is the development of a DVB-SH demodulator compliant with DVB-SH standard.
The s-band receiver chipset project objective is the development of a DVB-SH demodulator fully compliant with the DVB-SH standard. Moreover the demodulator is a multi-standard receiver capable of receiving DVB-SH, DVB-H and DVB-T signal.
The receiver development is targeted towards mobile reception, with integral support of code combining, antenna diversity and high Doppler resilience to enhance quality of reception in all conditions.
The receiver also supports the features newly added to the DVB-SH standard:
A prototype of the demodulator has been built based on FPGA architecture having the complete features of the demodulator available for field-testing as well as for laboratory performance tests.
The key issues addressed in the project are:
The main benefits of the project are:
The DVB-SH standard supports different system configurations (DVB-SHA, DVB-SHB), each with different profiles (Class-1 and Class-2 interleaver profiles), apart from this the DVB-SH standard defines the use of MPE-IFEC at the link layer, and the standard has been updated with support for low-latency services and extra bandwidths. Apart from this the receiver is a multi-standard receiver supporting DVB-H/DVB-T and DVB-SH.
To cope with all those requirements in a flexible way the receiver employs a flexible fully parameterizable architecture that has been extensively tested both in field trials and in laboratory. It has the following features:
The receiver architecture is targeted towards ASIC integration for mass-market production, but it also has FPGA technology in mind for initial evaluation/low volumes. Moreover an FPGA prototype has been developed to be able to exercise all the features of the receiver in field and lab tests.
The project is divided in three phases:
The project is completed.