- The primary objective of the SITKA project is the development of a Ka-band transceiver RF front end ASIC, intended for use in DTH satellite ground terminals, and situated within the Satellite Transceiver module. The ASIC will support GEO, MEO and LEO applications.
- The highly integrated ASIC will be designed to deliver more functionality for less power, and at a lower cost than current generation products, by taking full advantage of advanced RF CMOS silicon technology.
Technical challenges include the design of
- efficient Ka band pre-amplifiers in CMOS technology
- sufficient signal isolation on a single chip
- adequate phase noise for Ka-band operation
The SITKA single chip RF transceiver solution
- reduces component count and terminal cost
- uses less power to achieve the same RF functionality
- allows higher data rates due to Ka-band carrier capacity
Additionally, Ka-band operation facilitates terminal products in new and emerging markets.
The Sitka transceiver ASIC is designed to support frequency up- and down-conversion from I, Q baseband frequencies to Ka-band satellite carrier frequencies.
The ASIC supports
- dual polarisation
- full duplex Ka operation
- selection of carrier frequencies
- external programmability via SPI
A software GUI, source code and reference design PCB will be available to facilitate customer evaluation and product design in.
The key architectural features of the ASIC include
- Homodyne transmit and receive
- IF output for receive signals
- Trim-ability / optimization capability for all critical circuits
- Loopback for self-calibration
The project addresses the Technology Phase development and validation of a Ka-band Satellite Transceiver ASIC prototype.
The project is partitioned into 4 phases with milestones as follows
PDR: specifications and schematic design complete
CDR: mask / GDS design data complete
TRR: test hw/sw developed and prototypes fabricated
FDR: prototype characterisation reports generated.
- System and ASIC Specifications completed and released
- Schematic database completed
- Mask layout database in development
- First silicon on track for Q2, 2019
