ULtra fast Internet Satellite Switching (ULISS)


The main goal of the ULISS project is to prepare the future payloads for Multimedia missions in Ka Band, and more precisely, to fulfil four main objectives which are:

  • To define an advanced satellite system scenario (100 spotbeams, >20GHz of switched bands),
  • To demonstrate the feasibility of the corresponding Ultra Fast Packet Switch and enabling technologies,
  • To implement a new concept called the Radio Burst Switching (RBS), where the processing is devoted to the only demodulation /decoding of the header part of the packet,
  • To validate its performances in an existing DVB-RCS environment.

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A flexible routing and multiple QoS management schemes are also proposed (as packet switching improvements). The use of multi-giga bit link technology will be adopted to convey the data stream, for emulation of potential on board optical interconnects. Packet switch performance will be validated thanks to a real time traffic generator designed under a Hardware-in-the-loop design flow.


One of the major challenges of future telecommunication satellites is to efficiently provide wideband connectivity between a high number of user beams (~100 spotbeams, > 20GHz of switched bands).

Until now, flexible and dynamic switching systems such as regenerative packet switches have been band-limited, due to the constraints of embedded technology in charge of processing the whole data packet flow. Switching wider bands by satellite has meant reducing flexibility for the benefit of wideband transparent circuit switches - with a resulting reduction in reactivity and connectivity.


The project develops a new concept called the Radio Burst Switching (RBS), where the processing power is devoted only to the demodulation and decoding of the header part of the packet. Then, the system capacity is increased because the main burden of data flow is not processed (demodulation + decoding) but simply switched.

The proposed broadband system scenario, dealing with tens of GHz of switched bandwidth, was considered as unfeasible 5 years ago. Thanks to integrated multigigabit transceivers MGT and ASIC technology improvements, it can now be viewed as feasible and will be demonstrated into a realistic DVB-RCS environment.


The ULISS processor is composed of two main parts: the first one is in charge of the useful data (wideband transparent processing-oriented) and the second one (controller) deals with the header and signalling flow and is regenerative processing oriented.

A scaled-down version of the transparent switch has been prototyped in order to implement the key enabling technology and architecture of the full-scale version (hundred of Gbps of throughput), in particular implementing a high speed interconnect solution. The demonstrator includes innovative technologies like the 10G integrated transceivers (MGT) or System on Chip processing architecture (SoC)

Packet allocation and scheduling algorithm has been also designed and transposed into hardware with technological feasibility feedbacks. Innovative solutions for flexible QoS management have been proposed and mapped in a real time switch controller hardware.

An associated packet emulator with programmable traffic has been developed in order to feed data to the transparent switch and its controller. A packet analyser has been developed for performance measurements.

This demonstrator will be also designed to interface with an existing Thales Alenia Space DVB-RCS test bed (implementing Multi carrier packet demodulator and radio link emulator with DVB-RCS synchronization errors estimation on a ground –air loop).

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This project is 2 years and 4 months long, split in two phases.

Phase 1 deals first with the definition of a reference system scenario and the consolidation of the full-scale mesh processor architecture. Once the full-scale scenario is correctly defined, it shall provide the demonstrator specifications based on a scaled-down version of the full processor. The demonstrator definition, specification and architectural design will constitute the baseline for Phase 2.

Phase 2 aims at the detailed design and bit-true validation of the processor prototype. The ULISS demonstrator development will be concluded by a testing phase aimed to fully characterize the processor operations under the realistic system scenario defined in Phase 1.

Current status

Phase 1 has been successfully validated. The reference system scenario has been defined, including the on board processor architecture. A system simulator has been designed, providing the reference to be compared with the future real time demonstrator performances. The project has been extended to the related terminal, which includes device specification, end-to-end demonstration with representative propagation and synchronisation features.

Efficient upstream collaboration has enabled profitable design and cost savings, with a progressive integration approach. A specific effort has been put on the testing strategy, enabling the system simulator to generate also demonstrator configuration and test bench files.

The final boards version has been manufactured and are under testing. Multi gigabit electrical backplane interconnection are operational and the design of SoC FPGA are finished and successfully tested. FPGA and Board integration have started, gathering up to 4 nationalities contributions on some device. Final integration is planned for the second semester of 2008.

This project has received an innovation award from the Thales Alenia Space International Evaluation Committee.


Status date

Monday, November 1, 2010 - 13:49