Description
The objective of this activity is to develop the technology step needed to enable the use of optical interconnects at speeds of up to 112 Gbps. This should be demonstrated through testing of an integrated digital signal functions (ASIC and FPGAs) with the developed electro-optic transceiver photonic integrated circuits that form the optical I/Os to replace traditional electrical I/O.Targeted Improvements:Increase the data rate throughput up to 112Gbps per wavelength and through the technology change leverage a 30% power reduction (mW/Gbps) and size/mass reduction compared to today's solution.Description:Modern telecommunication satellites use onboard digital processors to be able to provide the increasing capacity to serve the economics of delivering traffic via space thatcustomers request. High throughput digital processors are the core of such payloads, capable of producing Tbps of intra-processor traffic. Enabling these large intra-processor traffic rates requires the most efficient interface technology possible, as power consumption and size are critical. A solution to this is the use of intra-processor optical interconnects to replace traditional electrical interconnects. The first operational satellite equipped with fibre optic interconnects running at 12.5 Gbps has been launched recently and this trend will only continue towards higher bit rates and higher integration of photonics within the processor equipment.In fostering this evolution, the Agency has funded the development of stand-alone optical transceivers operating at 28 Gbps and 56 Gbps for use in the next generation of processed payloads, representing the current state of the art for space applications. Payloadintegrators have stated the desire for optical interconnects that can operate at higher bit rates whilst also reducing the overall power consumption, volume, and mass of the onboard processors. To achieve this would be through the integration of the optical transceivers and the ASIC/FPGA in a single package. Various techniques would enable this, but no such development has been pursued so farfor use in space and any attempt will require the redesign of the circuits involved in order to meet the radiation susceptibility needs. The proposed activity would include a review of the electronic chips that will require and can support high throughput I/Os, the packaging techniques that can allow the integration of microelectronics and photonics, selection of the most appropriate baselinesolution and a demonstrator of suitable space ready solution of an ASIC/FPGA with 112 Optical I/Os.Procurement Policy: C(1) = Activity restricted to non-prime contractors (incl. SMEs). For additional information please go to:http://www.esa.int/About_Us/Business_with_ESA/Small_and_Medium_Sized_En…