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Objective: Identify and develop the architectural and algorithmic improvements necessary to enhance the performance of Digital Transparent Processors in terms of signal dynamic range, low noise, port bandwidth flexibility, robustness to interference, power consumption, etc.

Targeted Improvements: Improvement in dynamic range, noise level, robustness to interference and overall processor performance (power consumption and suitability for narrowband and asymmetric payloads).

Description: Recent developments of European transparent on-board digital processors have been focusing on increased bandwidth per input/output port and channelization/routing flexibility. The current generation of processors is particularly well suited for symmetric input/output ports (both in terms of number of ports and bandwidth per port).

Notwithstanding the remarkable performance achieved, improvements are necessary to maintain competitiveness in the area of narrow-band processors (e.g. MSS), to render transparent processors attractive for payload architectures where the number or the bandwidth of inputs/outputs is not symmetric (e.g. channelized payloads, multi-star payloads, MSS, etc.), toimprove signal quality performance (e.g. signal dynamic range, low noise, robustness to interference, etc.)

Focusing on narrowband and asymmetric port/bandwidth processors, the activity shall aim at identifying, defining and trading-off techniques and architectures in order to obtain the neededperformance enhancement.

In particular the following aspects shall be addressed:

  • Analyse contributions to signal quality and the changes necessary to improve end-to-end noise figure, dynamic range and robustness to interference (e.g. increased number of bits, improved LO phase noise for reduced aperture uncertainty at higher Nyquist zones, improved channelization algorithms, anti-clipping based processing techniques, narrow bandwidth/ high sampling rate converters, etc.).
  • Identify architectural/algorithmic upgrades to offer output port signals of variable bandwidth (to maximise the signal to beam allocation) allowing the optimisation of the DSP to reduce the power consumption and RF payload architecture complexity.

The study will demonstrate the key changes/developments via simulation and via a prototype board including EM-level for critical functions.





ARTES 5 Sub-El. 5.1

Price Range

200-500 KEURO

Tender Specifics

Eligibility: Austria, Belgium, Canada, Switzerland, Czech Republic, Germany, Denmark, Spain, France, Finland, United Kingdom, Italy, Ireland, Luxembourg, Norway, Netherlands, Portugal, Romania, Sweden
Open date: Monday, October 10, 2016
Closing date: Monday, May 15, 2017
Tender number: AO8796
Last Update Date: Friday, March 17, 2017
Update reason: Loaded a new Clarification(English version)