Objective: Identify and develop the architectural and algorithmic improvements necessary to enhance the performance of Digital Transparent Processors in terms of signal dynamic range, low noise, port bandwidth flexibility, robustness to interference, power consumption, etc.
Targeted Improvements: Improvement in dynamic range, noise level, robustness to interference and overall processor performance (power consumption and suitability for narrowband and asymmetric payloads).
Description: Recent developments of European transparent on-board digital processors have been focusing on increased bandwidth per input/output port and channelization/routing flexibility. The current generation of processors is particularly well suited for symmetric input/output ports (both in terms of number of ports and bandwidth per port).
Notwithstanding the remarkable performance achieved, improvements are necessary to maintain competitiveness in the area of narrow-band processors (e.g. MSS), to render transparent processors attractive for payload architectures where the number or the bandwidth of inputs/outputs is not symmetric (e.g. channelized payloads, multi-star payloads, MSS, etc.), toimprove signal quality performance (e.g. signal dynamic range, low noise, robustness to interference, etc.)
Focusing on narrowband and asymmetric port/bandwidth processors, the activity shall aim at identifying, defining and trading-off techniques and architectures in order to obtain the neededperformance enhancement.
In particular the following aspects shall be addressed:
The study will demonstrate the key changes/developments via simulation and via a prototype board including EM-level for critical functions.