Description
The objective of the activity is to develop, implement and test a 100 Gbps class interface radiation mitigation IP core for programmable logic devices for application in Low Earth and Geostationary Orbits. This includes hardware radiation characterisation and testing. Targeted Improvements: 3 to 4 times improvement of high-speed serial link data rate (from 32 Gbps to 112 Gbps) under radiation conditions. Description: State of the art programmable logic devices have the potential to enable high throughput nodes on satellites, machine-to-machine and internet of things applications on small platforms with limited resources, and wideband RF signal identification using machine learning. Powerful devices are available but are radiation sensitive.This activity will select and characterise relevant functional blocks of a state-of-the-art COTS programmable logic device with 100 Gbps class high bandwidth interfaces. A laboratory breadboard will be developed together with electrical ground support equipment (EGSE) suitable to perform radiation characterisation including Single Event Effects (SEE), Displacement Damage (DD) and Total Ionising Dose (TID). A radiation mitigation approach shall be developed and implemented in a radiation mitigation IP core in order to compensate for identified critical performance impacts. The device with the radiation mitigated IP core will be radiation tested and the performance will be compared to the unmitigated hardware performance.