Description
The objective of this activity is to design, manufacture and test a memory unit breadboard offering interface port and memory read and write speeds at 100 GigaBit per second and a capacity of at least 3 TeraBits for interconnected constellation telecommunication systems. Targeted Improvements: Improvement of the write speed by a factor of 10 compared to FLASH-based mass memories. Description:Future Low Earth Orbit (LEO) constellations with high-capacity interconnected satellite links require a data buffer function of at least 3 Terabits (Tb), combined with an interface and memory access speed of 100 Gigabit per second (Gbps) for reading and writing of the data. 100 Gbps write speed is difficult to achieve with FLASH-based mass memories.This activity will investigate and develop a memory module architecture that achieves 100 Gbps read and write speed and is modular and scalable to tens of Tb. Part of the trade-off will be the use of COTS memory devices such as Generation 4 of Double Data Rate (DDR) memory modules, but also DDR5/ GDDR6 devices. This includes implementing radiation effects mitigation techniques. A mass memory unit breadboarded and a testbed will be developed, manufactured and experimentally tested to evaluate the memory unit's performance, modularity and scalability.Footnote: On Delegation Request activities will only be initiated on the explicit request of at least one National Delegation.