Description
The objective of the activity is to develop and test a power-efficient, high-throughput and fault-tolerant network switching architecture for regenerative processors using COTS System-on-Chip (SoC) components as software-defined network switches. This will include radiation testing and development of fault mitigation methods (at system and software level). Targeted Improvements: Enabling reliable software-defined packet switching using COTS components. Description:On-board payload data handling systems for regenerative payloads will need to support tens to hundreds of individual channels and route a high number of packets with low latency to their destinations, whilst ensuring low packet loss through the network and keeping within a restricted power budget. Network switch components are important elements in packet routers. Commercial-off-the-shelf (COTS) System-on-Chip (SoC) components with multiple processors and high-speed interfaces could enable high-performance software-defined packet switching and reconfiguration of protocols in flight. In addition, such devices can offer additional processing capabilities within the payload. However, for COTS System-on-Chips, detailed SEE (Single-Event Effects) test results are currently not available. In addition, dedicated fault-mitigation techniques have yet to be developed. Due to the stringent requirements of availability and low loss of data in satellite communication applications, detailed knowledge of the failure modes of the COTS switch components must be obtained to appropriately mitigate such issues and enable fault-tolerant systems. In addition, at system level, it must be ensured that a permanent failure of a component does not disable an entire link and therefore dedicated redundancy and cross-strapping methods for network links shall be taken into account. This activity will evaluate COTS System-on-Chip devices that could be used for network switching. A network switching architecture and requirements for a representative satellite communication application will be defined and COTS System-on-Chip components that will potentially fulfill the defined requirements will be surveyed and traded-off for selection. In addition, the processing capabilities of the SoC devices shall be assessed as enablers for new functionalities (e.g., packet inspection). Radiation tests will be performed to characterise the selected device(s). Fault-tolerance techniques based on the error modes discovered by radiation testing will be derived, including system-level SEFI mitigation techniques to automatically recover the switching function in case of fault, including external monitoring circuits and real-time software monitoring of errors and housekeeping data (for example, the possibility to track the number of successful packets and act in case of a high number of errors on a link). A breadboard with multiple links and fault-mitigation features will be developed. The performance of the fault mitigation techniques deployed in the breadboard will be verified through fault injection and possible additional radiation testing. The radiation test results will be available for the Agency to distribute upon request to companies in ESA member states.