Description
The objective of the activity is to de-risk software mitigation techniques for radiation effects on a family of high-performance processors embedded in System on Chip (SoC) components. The activity will identify, on one or more processors of interest for the industry, radiation-induced failure modes and will implement appropriate software mitigation techniques with reuse or development of small FPGA IPs if needed. Targeted Improvements: Enable the use of commercial components with a 10- to a 100-fold increase in computingperformance (flops) and advanced features (like memory protection and virtualisation instructions).Description: A strong trend in the industry is to use Commercial-Off-The-Shelf (COTS) electronics, but their sensitivity to radiation is still a hurdle for industry-wide adoption. These radiation events can be tackled by appropriate countermeasures that are either fully software based or a combination of software and hardware functions. Some activities have been performed by ESA demonstrating the feasibility of this approach, including two in collaboration with CNES. An OSIP project is currently ongoing, and results are promising. The concepts need to be adapted to the COTS hardware used for telecommunication applications. Data from radiation tests of modern COTS devices are available and give confidence that some of them can reach the target in term of dependability once the mitigation techniques are applied.The activity will select the most promising and interesting COTS processing devices for telecommunication applications and implement dedicated radiation mitigation techniques. The prototype will demonstrate the feasibility and provide reliability and availability figures, as well as performance measurements supporting the reuse of this solution in future telecommunication payload processing units. The project will specify architecture(s) and develop prototype(s) of fault-mitigation functions in hardware and software, port representative telecommunication applications to these mitigated processors and validate the prototype(s) using fault injection and, if possible, radiation tests.