Description
The objective of this activity is the design, development and test of a more energy efficient receiver hardware architecture at system level. The activity shall include the investigation of more efficient receiver hardware design, use of narrower time slices and waveforms aimed at reducing demodulator complexity and produce a breadboard prototype.Targeted Improvements:50% energy reduction in receivers in TV broadcast and broadband user terminals.Description:In the last years, the satellite broadcasting industry in order to optimise the resource allocation has developed more complex waveforms to improve spectral efficiency at the expense of increased power use in receivers. For example, DVB-S2X was developed to enable the maximum possible spectral efficiency at the expense ofreceiver complexity and power consumption. In large geographic markets, such as Europe and North America, there are tens of millions of set-top boxes and a seemingly small power saving in each device can produce savings of the order of hundreds of MWs across the entire set-top box population.This activity will study an advanced waveform optimised for low-power consumption over spectral efficiency and perform system level trade-offs. Narrower time slices shall be investigated to reduce demodulator size requirement (although this might be at the expense of satellite multiplexing gains). Additionally, there is energy efficiency to be gained by removing conversion steps and complexity from the receiver hardware. The activity will include trade-offs, waveform design, system simulations, hardware development and testing of the new receiver architecture.