Description
Objective: The objective is to design, implement and test the IP Cores of the receiver for the coding and synchronisation layer of the two CCSDS telemetry waveforms for optical communications. Targeted Improvements: New market opportunities for optical terminal and equipment manufacturers, addressing both photon-starved links up to 8Gbps and high data rate links up to 10Gbps. This activity will target to reduce by 50% the development costs in future implementations of receivers in such applications. Description: The Consultative Committee for Space Data Systems (CCSDS) developed a dedicated telemetry waveform for optical links in a photon-starved regime, the so-called High Photon Efficiency (HPE) waveform. This has been recently complemented by another waveform for optical LEO direct-to-Earth links based on On-Off Keying (O3K), targeting a high data rate regime. The Coding Synchronisation layer of both waveforms performs functions such as randomisation, advanced Forward Error Correction (FEC) coding, long channel interleaving, framing, and signalling to implement a pulsed binary modulation at the physical layer. The specification covers a wide range of symbol rates (up to 10 Gsym/s). While the HPE standard is already public, the O3K standardisation process is currently being finalised. However, IP cores for both HPE and O3K transmitters will be made available in the ESA IP core portfolio by the end of the year. The objective of this activity is the design, implementation and test of Intellectual Property (IP) Cores implementing the receiver for CCSDS HPE and O3K Coding Synchronisation specifications. The development of such IP Cores will foster space-based optical communication and are needed for the development of optical onboard terminals and ground segment. The HPE/O3K receiver IP Cores shall be implemented using synthesizable hardware description language (HDL). It shall be technology independent, implementable in different application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA) technologies. The receiver IP Cores shall be validated by simulation.