Description
The objective of the activity is to identify and benchmark power efficient radio frequency algorithms on complex System on Chip (SoC) devices. Power efficient algorithms for at least two applications case (e.g. beamforming, decoding/encoding, neural networks...) will be designed, developed and tested and compared to programmable logic only implementation.Targeted Improvements: 50% reductionpower consumption for radio frequency algorithms with respect to programmable logic only implementation.Description: The latest system on chip devices employing ultra-deep submicron technology offers the possibility to improve the power efficiency of high throughput and regenerative payloads. Power efficiency improvements up to 50% are now in reach for many on-board applications. However, this also requires power efficient, tailored algorithms not existing today.This activity will investigate existing algorithms and design and develop tailored, power efficient algorithms for at least two on-board applications (e.g. beamforming, decoding/encoding, neural networks...). Each developed algorithm will be tailored, implemented and tested in a selected SoC and compared to a reference.One candidate SoC technology considered for the implementation shall be a 7nm silicon node system or equivalent. A combined hardware and software testbed shall be developed allowing for accurate performance evaluation including DC power and throughput measurements.