Digital Transparent Processor (DTP)

Objectives

The objective of the project is the design, development and test of a Digital Transparent Processor based on an EQM model.
The DSP is designed to provide flexible channelization and transparent routing capability for advanced space telecommunication applications.

The main features of the development are:

  • The design of a DTP with a modular architecture enabling the reuse of major building blocks (ASICs and boards) for various capacity DTPs. This is implemented thanks to appropriate equipment architecture based on modular mechanical packaging.
  • The development of generic signal processing ASICs permiting to have a modular approach, fully compatible with different bandwidth and capacity (standardization product approach).
  • The EQM with limited capacity allows for a piggy back mission in order to:
    • Complete the on-ground qualification of new technologies by an in-orbit qualification,
    • Give the operator the opportunity to operate the DTP on a reduced part of the payload bandwidth.
  • This standardization approach is an important step for high density digital products (DTP, on board regenerative processor, etc.).

The choice for an EQM quality level guarantees a full qualification of technologies, parts, manufacturing processes and unit design.


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Challenges

DTP is a key product in mobile payload or flexible payload, either in Ka or Ku band, and for both civilian or for military applications.

For multibeam applications, the DTP is an important component, permitting to adapt and route the traffic according to the market needs.

The developed product can be the core of future payload, featuring customers in-coming expectations in term of frequency plan flexibility, high connectivity capacity, low granularity and broadcast or multicast capability.

Benefits

New flexibility for telecom satellite systems and payloads, thanks to high capacity and versatility in on board processors.

Independency to the mission: transparent on board processors offer the possibility to be waveform independent.

Features

The architecture of the DTP breaks down into:

  • Analogue front end and associated ADC and DAC converters,
  • The channelization function performing fine digital filtering of sub-channels. Sub-channels bandwidth is variable and programmable by ground commands. The channelization function is based on a demultiplexer/multiplexer ASIC in the last available space qualified technology.
  • The switch function performs a full connectivity routing at sub-channel level between the input and output ports. Main characteristics of the switch are:
    • Frequency and spatial routing,
    • Non blocking switching capability,
    • Broadcast and multicast capability.
  • The DCDC function distributes the power supply to the different boards of the unit.
  • The TMTC function is in charge of the command and control of the processor. It mainly controls the following parameters of the unit:
    • The redundancy scheme,
    • The switching plan,
    • The gain plan.
  • The Clock function distributes the sampling and processing clocks.

The power bus and TMTC bus interfaces are compliant with SPACEBUS 4000 or ALPHABUS requirements and could also be easily adapted to any other buses.

Plan

The EQM activities are organized in two phases:

Phase 1:

Key milestones of phase 1 are the Baseline Design Review (BDR) at T0+3 months and the MTR (Mid Term Review) at T0+12 months:

  • At the BDR, the EQM unit preliminary architecture is presented together with the targeted performance and specifications.
  • At the MTR, architectural design, detailed design and technologies qualification will be over. This review will allow to summarize the phase 1 results and demonstrate the ability of the design to meet the technical requirements. In addition the qualification test procedure will be presented.

Phase 2:

This phase starts after the MTR meeting and ends with the FR (Final Review). Following tasks are driven:

  • Prototypes ASIC manufacturing,
  • Boards manufacturing and testing,
  • EQM manufacturing, integration and validation,
  • EQM acceptance tests.

The key milestone of phase 2 is the FR. During this review, acceptance tests results will be presented and compliance with requirements reviewed.

Current status

  • Manufacturing and test of the EQM has been completed,
  • Final Review held.

Contacts

Status date

Thursday, January 13, 2011 - 17:46