The availability of an autonomous mean of positioning in a geostationary platform is essential in reducing the dependence on the ground control, especially when low-thrust electrical propulsion is used to transfer the satellites to the GEO orbit, a manoeuvre that lasts several months. In this case, the on-board GNSS function can autonomously feed the avionic systems in charge of controlling the trajectory and the attitude, and schedule in this way the requested thrusters actuations and attitude variations.
Nowadays the use of GNSS Receivers in GEO satellites is a reality, although their cost is quite high. The first part of the project has been focused on the cost-wise analysis of the architecture of a GNSS receiver to identify the potential areas where a significant reduction of the recurring cost can be achieved.
In the second part, a novel architecture of the RF-IF section of the receiver has been designed and manufactured using a highly integrated solution based on a hybrid RF-digital MMIC developed for this purpose in the frame of the project.
Finally an elegant breadboard incorporating both the RF-IF section and an AGGA-4-based digital board has been assembled and tested to verify the overall performance of the GNSS receiver.
- Revisit current navigation receiver implementations for GEO satellites to define an architecture and physical implementation compatible with the target cost of 200 k€ for the final space qualified flight model.
- Develop an elegant breadboard implementing an innovative, highly integrated RF-IF section using a new hybrid RF-digital MMIC design.
A highly integrated RF-IF section allows to significantly reduce the overall cost of the receiver both in terms of components and in terms of manufacturing and test.
The RF/IF MMIC is a SiGe BiCMOS GNSS Dual Channel Receiver especially designed for E5a and L1 simultaneous dual Carrier reception. The MMIC may operate as RF amplifier followed by a low IF down converter for GNSS Navigation Signals;
The undersampling conversion scheme guarantees extremely low power consumption and lower Phase Noise compared to a direct down converter in L band.
The Digital section of the GNSS receiver is based on ESA AGGA4 ASIC. This device hosts two main functional blocks:
- The GNSS Core, that implements the correlation function on incoming digital stream from the ADC (RF section); up to 32 Single Frequency / Double Code GNSS Channels are available.
- The LEON2 Fault-Tolerant processor, based on SPARC V8 architecture.
In addition, the Digital section houses the boot PROM storing configuration and basic code, program EEPROM for application SW and data permanent storage, data and program RAM.
Real Time Navigation Data (Position, Velocity, Time), as well as basic house-keeping telemetry, are provided to in output through the communication interface. An additional output is the PPS. Two antennas are used to increase the SV visibility during the different orbital conditions.
The Elegant Breadboard designed and developed in the frame of the project consist of a RF-IF section, based on a highly integrated MMIC designed and manufactured ad hoc, and of a digital section based on AGGA-4 processor. These two sections represent the core elements of a GNSS receiver and allow to verify the overall performance.
The project started in May 2017 and is split into three phases.
Phase 1: architectural trade-off, receiver specifications and preliminary design. Phase 1 ended with Preliminary Design Review, held in November 2017
Phase 2: EBB detailed design (RF-IF board and digital board) and MMIC manufacturing. Phase 2 ended with Detailed Design Review, concluded in July 2018.
Phase 3: RF-IF Board manufacturing and test and EBB integration and performance test. Test Review Board held on June 2020.
The duration of phase 3 has been affected by the COVID-19 pandemic.
The project has been completed.