The Project was planned within two consecutive Tasks. Task 1 included all the system definition work, different LO solutions were investigated and the requirement specifications updated (VCO and PLL EM unit). Also technology trade off for the VCO topologies, VCO semiconductor process and foundry were performed in task 1. The task ended with a technology trade off review in October 2014. Task 2 included detailed design, manufacturing, integration and test for the VCO MMIC and PLL EM Unit, and ended in January 2017.
Most significant achievements of the project
- Three different VCO versions in the chosen GaN technology process has been designed, evaluated and tested.
- One PLL EM Unit designed, manufactured and tested to show function and performance of the VCO.
The measured main parameters including
- Phase noise
- LO Harmonics
- Spurious at LO output (f/2, 3f/2, 5f/2, 100 MHz ref.)
- VCO tuning range (up to +60 V)
- Loop Band Width
- Output power (+12.5 - 13.5 dBm)
were within specified limits as set up for the PLL EM Unit. Measured Phase Noise is as expected and in line with calculations. The VCO tuning range was sucessfully extended (up to +60 V) by design of a new loop filter.
However the current status for the GaN technology is that it suffers from high 1/f noise which significantly degrades the phase noise performance.
The most significant achievements of the project also involve higher understanding of VCO design and modelling in general, and special in design and manufacturing a MMIC VCO using GaN technology.
A GaN varactor model based on measurements and suitable for phase noise simulations was also developed within the project and possible through the close cooperation with Chalmers University.