Description
The objective of the activity is to design, manufacture and test a prototype of an on-board timing equipment for secure communications. Targeted Improvements: Enabling secure communications thanks to high accuracy and resilient timing synchronisation (sub micro seconds). Description:Governmental communications make use of secured waveforms, which implement modern techniques like frequency hopping or direct sequence spread spectrum, and require a high level of performance for modem and network synchronisation. Current on-board synchronisation technologies based on quartz oscillators do not provide the required timing accuracy and robustness for such critical missions. The use of local oscillators disciplined to GNSS can achieve such performance requirements, but it can be subject to attacks such as GNSS jamming, deteriorating their performance. There is thus a need for more robust, high performance time synchronisation for secured communications.The introduction of solutions based on a combination of technologies (quartz oscillator, GNSS, chipscale atomic clock) with associated algorithms for control and integrity, offers the possibility to contemplate both high level of performance, with a high level of resilience.In this activity it is proposed to perform the design, development and testing of a robust on-board timing solution. System aspects related to time synchronisation, in particular modem and network synchronisation, shall be considered as part of the design and a security risk analysis shall be performed to assess the necessary level of resilience needed for governmental communications (e.g. holdover period versus performance). A breadboard prototype, encompassing all critical components of the equipment, will then be tested and validated to demonstrate the required performance.