Description
The objective of the activity is to design, develop and test a very low Size, Mass and Power (SWaP) device able to assure time and frequency stability from one to two order of magnitudes better than high performance devices (e.g. oven cooked crystal oscillators).Targeted Improvements: Reduce the power consumption down to 100 mW for portable terminals.Description: Governmental communications feature the need to have high-performance synchronisation performance due to the use of complex waveforms, typically involving spread spectrum (direct sequence or frequency hopping). A highly accurate time reference becomes critical; to answer this need chip-Scale atomic clocks (CSAC) exist in the commercial market, in particular US products are available also for space applications. However, the available products in Europe are lacking behind in terms of power consumption, restricting some usages such as portable critical applications, in which external synchronisation may not be sufficient or not enough reliable. A power consumption reduction below100 mW could enable these new usages and the feasibility of reaching such performance was demonstrated on paper through past ESA activities. The present activity will aim to perform the design, prototyping and testing of a time reference component able to addressportable terminals secure communications. The activity shall address in particular the optimisation of the design, addressing thermal design, electronic and packaging so to define a design baseline and prove that performances are not compromised. A prototype, corresponding to TRL5, shall be developed.